projects / platform / kernel / linux-rpi.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 20183cc) | patch
tools/power/x86/intel-speed-select: Display TRL buckets for just base config level
authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Wed, 20 Nov 2019 00:22:54 +0000 (16:22 -0800)
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Thu, 21 Nov 2019 12:31:34 +0000 (14:31 +0200)
commit1434a3d357d656d4b11fcbdc9b6c35dc673292a0
treef049f8e4933a3a877eedbcfc6d96737b6075ab4ftree | snapshot
parent20183ccd3e4d01d23b0a01fe9f3ee73fbae312facommit | diff
tools/power/x86/intel-speed-select: Display TRL buckets for just base config level

When only base config level is present, this tool is displaying TRL
(Turbo-ratio-limits) by reading legacy MSR. In this case, also present
core count for TRL by reading MSR 0x1AE.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
tools/power/x86/intel-speed-select/isst-core.c diff | blob | history
Domain: System / Kernel;