drm/msm/a5xx: fix highest bank bit for a530
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tue, 14 Feb 2023 02:09:54 +0000 (05:09 +0300)
committerRob Clark <robdclark@chromium.org>
Wed, 22 Feb 2023 19:22:03 +0000 (11:22 -0800)
commit141f66ebbfa17cc7e2075f06c50107da978c965b
tree9b312a3a25d1bf8442ff877cc6492611b8d7c91f
parenta7a4c19c36de1e4b99b06e4060ccc8ab837725bc
drm/msm/a5xx: fix highest bank bit for a530

A530 has highest bank bit equal to 15 (like A540). Fix values written to
REG_A5XX_RB_MODE_CNTL and REG_A5XX_TPL1_MODE_CNTL registers.

Fixes: 1d832ab30ce6 ("drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/522639/
Link: https://lore.kernel.org/r/20230214020956.164473-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a5xx_gpu.c