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arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types
authorBiju Das <biju.das.jz@bp.renesas.com>
Tue, 2 Aug 2022 10:15:33 +0000 (11:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 22 Aug 2022 07:46:03 +0000 (09:46 +0200)
commit13dec051c7f139eef345c55a60941843e72128f1
treef4267da3670896be04be8c0546f86757a10c6c8ftree | snapshot
parentf3b7bc89c97b98aa6f157d5f296695af8940a5accommit | diff
arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types

As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021),
the interrupt type of SCI{Rx,Tx} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a07g054.dtsi diff | blob | history
Domain: System / Kernel;