powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
authorScott Wood <scottwood@freescale.com>
Fri, 12 Oct 2012 23:02:24 +0000 (18:02 -0500)
committerScott Wood <scottwood@freescale.com>
Mon, 26 Nov 2012 21:41:27 +0000 (15:41 -0600)
commit13d1143ffb4dc0c71478534b6b52402e95be9420
tree0fb8cac0505d385547eb44f4c4afc35165ac7e62
parentd674bccf738396ecdc4374f5b5cb3e7fd376a0ab
powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data.  The SPL itself cannot use SPD due
to code size constraints.  It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with.  It's possible that different revisions of the board
require different settings.  Using SPD eliminates that problem.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
board/freescale/p1_p2_rdb_pc/ddr.c
board/freescale/p1_p2_rdb_pc/spl_minimal.c
board/freescale/p1_p2_rdb_pc/tlb.c
include/configs/p1_p2_rdb_pc.h