Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
authorHans Wennborg <hans@hanshq.net>
Thu, 19 Sep 2019 12:33:07 +0000 (12:33 +0000)
committerHans Wennborg <hans@hanshq.net>
Thu, 19 Sep 2019 12:33:07 +0000 (12:33 +0000)
commit13bdae8541c3fc5acf6ee7de78ec5ab8446848e4
tree669a6f1688a221bbe583395a729990cd90acf442
parent0cfb78e52af247366e6e8fe00a906022bf4abca5
Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"

This broke the Chromium build, causing it to fail with e.g.

  fatal error: error in backend: Cannot select: t362: v4i32 = X86ISD::VSHLI t392, Constant:i8<15>

See llvm-commits thread of r372285 for details.

This also reverts r372286, r372287, r372288, r372289, r372290, r372291,
r372292, r372293, r372296, and r372297, which seemed to depend on the
main commit.

> Encode them directly as an imm argument to G_INTRINSIC*.
>
> Since now intrinsics can now define what parameters are required to be
> immediates, avoid using registers for them. Intrinsics could
> potentially want a constant that isn't a legal register type. Also,
> since G_CONSTANT is subject to CSE and legalization, transforms could
> potentially obscure the value (and create extra work for the
> selector). The register bank of a G_CONSTANT is also meaningful, so
> this could throw off future folding and legalization logic for AMDGPU.
>
> This will be much more convenient to work with than needing to call
> getConstantVRegVal and checking if it may have failed for every
> constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth
> immarg operands, many of which need inspection during lowering. Having
> to find the value in a register is going to add a lot of boilerplate
> and waste compile time.
>
> SelectionDAG has always provided TargetConstant for constants which
> should not be legalized or materialized in a register. The distinction
> between Constant and TargetConstant was somewhat fuzzy, and there was
> no automatic way to force usage of TargetConstant for certain
> intrinsic parameters. They were both ultimately ConstantSDNode, and it
> was inconsistently used. It was quite easy to mis-select an
> instruction requiring an immediate. For SelectionDAG, start emitting
> TargetConstant for these arguments, and using timm to match them.
>
> Most of the work here is to cleanup target handling of constants. Some
> targets process intrinsics through intermediate custom nodes, which
> need to preserve TargetConstant usage to match the intrinsic
> expectation. Pattern inputs now need to distinguish whether a constant
> is merely compatible with an operand or whether it is mandatory.
>
> The GlobalISelEmitter needs to treat timm as a special case of a leaf
> node, simlar to MachineBasicBlock operands. This should also enable
> handling of patterns for some G_* instructions with immediates, like
> G_FENCE or G_EXTRACT.
>
> This does include a workaround for a crash in GlobalISelEmitter when
> ARM tries to uses "imm" in an output with a "timm" pattern source.

llvm-svn: 372314
79 files changed:
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/lib/Target/AMDGPU/BUFInstructions.td
llvm/lib/Target/AMDGPU/DSInstructions.td
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td
llvm/lib/Target/Hexagon/HexagonDepOperands.td
llvm/lib/Target/Hexagon/HexagonIntrinsics.td
llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
llvm/lib/Target/Mips/Mips64InstrInfo.td
llvm/lib/Target/Mips/MipsDSPInstrInfo.td
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/lib/Target/SystemZ/SystemZInstrVector.td
llvm/lib/Target/SystemZ/SystemZOperands.td
llvm/lib/Target/SystemZ/SystemZOperators.td
llvm/lib/Target/SystemZ/SystemZPatterns.td
llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyInstrBulkMemory.td
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrMMX.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86InstrSystem.td
llvm/lib/Target/X86/X86InstrTSX.td
llvm/lib/Target/X86/X86InstrXOP.td
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll [deleted file]
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir [deleted file]
llvm/test/TableGen/immarg.td [deleted file]
llvm/utils/TableGen/GlobalISelEmitter.cpp