[VTA][Chisel] TSIM VTA Source Refactor (#4163)
authorBenjamin Tu <tu.benjamin1115@gmail.com>
Sun, 27 Oct 2019 00:06:49 +0000 (17:06 -0700)
committerJared Roesch <roeschinc@gmail.com>
Sun, 27 Oct 2019 00:06:49 +0000 (17:06 -0700)
commit13b2856616981ee92182bb3edece4936c182a86b
tree4b89143bc488391dbbe6db7480a7277ed37adf7a
parent07606e4cb4e7354e393ec8dbf1fa20c5fe35b0db
[VTA][Chisel] TSIM VTA Source Refactor (#4163)

* app init push

* fix on readme

* change name, add bit serial explanantion

* rm serialLoadMM, change doc

* syntax change for readme

* add parallel test functionality

* fix readme

* add python doc

* syntax

* init commit

* fix empty line

* fix typo
vta/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala
vta/apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala
vta/apps/gemm/src/driver.cc
vta/apps/gemm/tests/python/chisel_accel.py