projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 47800a1) | patch
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X...
authorCraig Topper <craig.topper@sifive.com>
Tue, 23 May 2023 16:19:37 +0000 (09:19 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 23 May 2023 16:19:55 +0000 (09:19 -0700)
commit139392c0a58008b7451e1a1943f5022dc920928b
tree2b0d4d9f7c5e13708e7fc2cdcdbd689f15d66eb0tree | snapshot
parent47800a12dcb4cb6fee395f86cb7a81aa3fb4b932commit | diff
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.

We can compute a simpler expression for Lo for these cases. This
is an alternative for the test cases in D151180 that works for
more targets.

This is similar to some of the special cases we have for expanding
setcc operands.

Differential Revision: https://reviews.llvm.org/D151182
12 files changed:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp diff | blob | history
llvm/test/CodeGen/AArch64/fpclamptosat.ll diff | blob | history
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll diff | blob | history
llvm/test/CodeGen/ARM/fpclamptosat.ll diff | blob | history
llvm/test/CodeGen/ARM/fpclamptosat_vec.ll diff | blob | history
llvm/test/CodeGen/RISCV/fpclamptosat.ll diff | blob | history
llvm/test/CodeGen/RISCV/min-max.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll diff | blob | history
llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll diff | blob | history
llvm/test/CodeGen/VE/Scalar/smax.ll diff | blob | history
llvm/test/CodeGen/WebAssembly/fpclamptosat.ll diff | blob | history
llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll diff | blob | history
Domain: System / Toolchain;