[PowerPC] Add vector pair load/store instructions and vector pair register class
authorBaptiste Saleil <baptiste.saleil@ibm.com>
Mon, 21 Sep 2020 15:23:51 +0000 (10:23 -0500)
committerBaptiste Saleil <baptiste.saleil@ibm.com>
Mon, 21 Sep 2020 15:27:47 +0000 (10:27 -0500)
commit1372e23c7d4b25fd23689842246e66f70c949b46
treee87d9c5d0b8a505a002e64e220fa2d33392a64b1
parent5249e6f24876ea577de51ad2f9166a2e466171b9
[PowerPC] Add vector pair load/store instructions and vector pair register class

This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.

Differential Revision: https://reviews.llvm.org/D84359
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
llvm/utils/TableGen/CodeGenTarget.cpp