drm/amd/display: treat memory as a single-channel for asymmetric memory V3
authorHugo Hu <hugo.hu@amd.com>
Wed, 21 Apr 2021 06:23:44 +0000 (14:23 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 20 May 2021 02:38:24 +0000 (22:38 -0400)
commit132c894e93f18cf3b943753063bb0fd6ca8483ac
treeb0d7de24b8ad08b484700a823ae1c04edaddca6e
parent5709121a58a21e0bbde362536ec456f1a64c4ec4
drm/amd/display: treat memory as a single-channel for asymmetric memory V3

Previous patch caused crash and had been reverted. This patch
addresses the issue without regression.

[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.

[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dc.h