MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler
authorPaul Burton <paul.burton@mips.com>
Tue, 1 Oct 2019 21:53:42 +0000 (21:53 +0000)
committerPaul Burton <paul.burton@mips.com>
Mon, 7 Oct 2019 16:43:09 +0000 (09:43 -0700)
commit12dbb04f2ac1fcbef0d6463abb3071ce8d8fe45f
tree09b1a1b5d7d35db3a5a20cec5a5cab111a6fca92
parentae4cd0b1a4756344cb99c0004d156b585cf9e907
MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler

In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
arch/mips/kernel/genex.S