drm/i915: program drain latency regs on ValleyView
authorGajanan Bhat <gajanan.bhat@intel.com>
Wed, 28 Mar 2012 20:39:30 +0000 (13:39 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 28 Mar 2012 21:55:36 +0000 (23:55 +0200)
commit12a3c0551137425a9678d1b9f0495b625550f092
tree96f0dfa07499e8defc100db3dcc0782bc60a7f7b
parentfb046853ad66e64c96a2598f3fdd4cf5fbabc0d1
drm/i915: program drain latency regs on ValleyView

This patch adds support for programming drain latency registers of Pondicherry
memory arbiter of Valleyview.

v2: clarify function names (Daniel)
    fix summary typo (Daniel)
v3: add parens (Ben)
    make drain function return bool (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c