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[RISCV] Improve extract_vector_elt for fixed mask registers.
authorjacquesguan <Jianjian.Guan@streamcomputing.com>
Sat, 15 Jan 2022 09:14:38 +0000 (17:14 +0800)
committerjacquesguan <Jianjian.Guan@streamcomputing.com>
Sat, 29 Jan 2022 03:07:53 +0000 (11:07 +0800)
commit1276678982a0c9d0d7aba6afdc83d34ee42f397c
tree5db5c0235c0202105a46dcba0ef831b9481fc3a2tree | snapshot
parentbf4cab29f5a88b622e200d59d9156f2ca31165ebcommit | diff
[RISCV] Improve extract_vector_elt for fixed mask registers.

Now the backend promotes mask vector to an i8 vector and extract element from that. We could bitcast to a widen element vector, and extract from it to GPR, then use I instruction to extract the certain bit.

Differential Revision: https://reviews.llvm.org/D117389
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll diff | blob | history
Domain: System / Toolchain;