review.tizen.org Git - platform/upstream/tvm.git/commit

projects / platform / upstream / tvm.git / commit

author	Luis Vega <vegaluisjose@users.noreply.github.com>
	Tue, 11 Jun 2019 23:55:41 +0000 (16:55 -0700)
committer	Thierry Moreau <moreau@uw.edu>
	Tue, 11 Jun 2019 23:55:41 +0000 (16:55 -0700)
commit	124f9b7f7c46fd168c892ecc13676974732ad9f2
tree	a6b5b74f4828184ae3b5f71c2553e401533dca66	tree \| snapshot
parent	2c41fd2f038e90539479ab08370916c1ecd95d2b	commit \| diff

[VTA][TSIM] update app example (#3343)

* add initial support to cycle counter to accelerator

* remove prints from c

* add event counter support to chisel tsim example

* make it more readable

* use a config class

* update driver

* add individual Makefile to chisel

* add rule for installing vta package

* add makefile for verilog backend

* update drivers

* update

* rename

* update README

* put default sim back

* set counter to zero

22 files changed:

vta/apps/tsim_example/CMakeLists.txt		diff \| blob \| history
vta/apps/tsim_example/Makefile		diff \| blob \| history
vta/apps/tsim_example/README.md		diff \| blob \| history
vta/apps/tsim_example/cmake/modules/hw.cmake	[deleted file]	blob \| history
vta/apps/tsim_example/config/config.json	[deleted file]	blob \| history
vta/apps/tsim_example/config/config.py	[deleted file]	blob \| history
vta/apps/tsim_example/hardware/chisel/Makefile		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala		diff \| blob \| history
vta/apps/tsim_example/hardware/verilog/Makefile	[new file with mode: 0644]	blob
vta/apps/tsim_example/hardware/verilog/src/Accel.v	[moved from vta/apps/tsim_example/hardware/verilog/Accel.v with 63% similarity]	diff \| blob \| history
vta/apps/tsim_example/hardware/verilog/src/Compute.v	[moved from vta/apps/tsim_example/hardware/verilog/Compute.v with 85% similarity]	diff \| blob \| history
vta/apps/tsim_example/hardware/verilog/src/RegFile.v	[moved from vta/apps/tsim_example/hardware/verilog/RegFile.v with 72% similarity]	diff \| blob \| history
vta/apps/tsim_example/hardware/verilog/src/TestAccel.v	[moved from vta/apps/tsim_example/hardware/verilog/TestAccel.v with 100% similarity]	blob \| history
vta/apps/tsim_example/python/accel/__init__.py	[moved from vta/apps/tsim_example/python/tsim/__init__.py with 100% similarity]	blob \| history
vta/apps/tsim_example/python/accel/driver.py	[moved from vta/apps/tsim_example/python/tsim/driver.py with 62% similarity]	diff \| blob \| history
vta/apps/tsim_example/src/driver.cc		diff \| blob \| history
vta/apps/tsim_example/tests/python/chisel_accel.py	[moved from vta/apps/tsim_example/tests/python/add_by_one.py with 71% similarity]	diff \| blob \| history
vta/apps/tsim_example/tests/python/verilog_accel.py	[moved from vta/apps/tsim_example/cmake/modules/sw.cmake with 56% similarity]	diff \| blob \| history
vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v		diff \| blob \| history
vta/hardware/dpi/tsim_device.cc		diff \| blob \| history

Domain: Machine Learning / ML Framework;

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