Bias physical register immediate assignments
authorNirav Dave <niravd@google.com>
Wed, 14 Nov 2018 21:11:53 +0000 (21:11 +0000)
committerNirav Dave <niravd@google.com>
Wed, 14 Nov 2018 21:11:53 +0000 (21:11 +0000)
commit1241dcb3cf469c3de9c5ca35af0a64fbb69cc10b
tree7d6902d1305394b284b1709dff6e0b997a9888c6
parentb0486051d29086f48f3c0db469c1e88747a21057
Bias physical register immediate assignments

The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.

This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out-of-registers
assertion (PR39391).

Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.

Reviewers: MatzeB, qcolombet, myatsina, pcc

Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya,
  javed.absar, arphaman, jfb, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D54218

llvm-svn: 346894
42 files changed:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
llvm/test/CodeGen/AMDGPU/local-atomics64.ll
llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
llvm/test/CodeGen/AMDGPU/ret.ll
llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
llvm/test/CodeGen/X86/anyext.ll
llvm/test/CodeGen/X86/atomic_mi.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/CodeGen/X86/bss_pagealigned.ll
llvm/test/CodeGen/X86/bypass-slow-division-32.ll
llvm/test/CodeGen/X86/bypass-slow-division-64.ll
llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
llvm/test/CodeGen/X86/cmpxchg16b.ll
llvm/test/CodeGen/X86/code-model-elf-memset.ll
llvm/test/CodeGen/X86/combine-srem.ll
llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
llvm/test/CodeGen/X86/divrem.ll
llvm/test/CodeGen/X86/known-bits.ll
llvm/test/CodeGen/X86/machine-cse.ll
llvm/test/CodeGen/X86/memset-nonzero.ll
llvm/test/CodeGen/X86/misched-code-difference-with-debug.ll
llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/patchpoint.ll
llvm/test/CodeGen/X86/pr32282.ll
llvm/test/CodeGen/X86/pr36865.ll
llvm/test/CodeGen/X86/pr38865.ll
llvm/test/CodeGen/X86/scalar_widen_div.ll
llvm/test/CodeGen/X86/shrink_vmul-widen.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/speculative-load-hardening.ll
llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
llvm/test/DebugInfo/X86/live-debug-values.ll