i965: Enable L3 caching of buffer surfaces.
authorFrancisco Jerez <currojerez@riseup.net>
Tue, 16 Dec 2014 14:11:57 +0000 (16:11 +0200)
committerFrancisco Jerez <currojerez@riseup.net>
Sat, 31 Jan 2015 15:01:49 +0000 (17:01 +0200)
commit11f5d8a5d4fbb861ec161f68593e429cbd65d1cd
tree82973704141d16da0d20061a97602d9de37d5399
parent11a955aef42730ab009490f03c03c54ed07db666
i965: Enable L3 caching of buffer surfaces.

And remove the mocs argument of the emit_buffer_surface_state vtbl hook.  Its
semantics vary greatly from one generation to another, so it kind of
encourages the caller to pass 0 which is the only valid setting across
generations.  After this commit the hardware-specific code decides what the
best cacheability settings are for buffer surfaces, just like we do for
textures.

This together with some additional changes coming is expected to improve
performance of pull constants, buffer textures, atomic counters and image
objects on Gen7 and up.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
src/mesa/drivers/dri/i965/gen8_surface_state.c