iommu/amd/pgtbl_v2: Fix domain max address
authorVasant Hegde <vasant.hegde@amd.com>
Thu, 18 May 2023 05:43:51 +0000 (05:43 +0000)
committerJoerg Roedel <jroedel@suse.de>
Tue, 23 May 2023 06:29:25 +0000 (08:29 +0200)
commit11c439a19466e7feaccdbce148a75372fddaf4e9
treeb1fdc274ac2fb0377d27ccca4997257e809646bf
parent2212fc2acf3f6ee690ea36506fb882a19d1bfcab
iommu/amd/pgtbl_v2: Fix domain max address

IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual
address space. Current code assumes it can support 64bit IOVA address
space. If IOVA allocator allocates virtual address > 47/56 bit (depending
on page table level) then it will do wrong mapping and cause invalid
translation.

Hence adjust aperture size to use max address supported by the page table.

Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table")
Cc: <Stable@vger.kernel.org> # v6.0+
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230518054351.9626-1-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd/iommu.c