TEST mfld pmu: add include/linux/intel_mid_pm.h -- for now

TEST mfld pmu: add include/linux/intel_mid_pm.h -- for now

needed to compile mfld pmu driver

from UMG 2.6.35 tree:

commit 1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Thu Jun 23 04:58:43 2011 +0530

    mid_pmu:  sparse warnings fixed

    BZ: 3856

    Fixed the following sparse warnings.

    arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?

    fixed make namespacecheck issues.

    Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 0704c9bfd967b44da1e61a05f8789052bc6fbd29
Author: Sujith Thomas <sujith.thomas@intel.com>
Date:   Wed May 25 14:55:42 2011 +0530

    mid_pmu: Defining the OSPM macros to handle CONFIG_INTEL_MID_PM disabled

    BZ: 1957

    Currently the OSPM macros are not defined during CONFIG_INTEL_MID_PM disabled.
    This is breaking the compilation in Gfx and ISP drivers whenc CONFIG_PM is disabled.

    Now the OSPM macros are defined irrespective of CONFIG_INTEL_MID_PM flag.

    Change-Id: I6cf6185d712b728e5733c473d8a2947c36c62e03
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit 5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date:   Thu Jun 16 16:59:39 2011 -0700

    Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
    of talking to P-unit and getting the corresponding power islands to ON/OFF.
    Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
    Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit 53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon May 16 00:26:13 2011 +0530

    mid_pmu: demote c6 to c4 while s0ix is in progress

    BZ: 2120

    While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
    mwait and since the SCU is still waiting for Ack_C6 the S0ix
    ACK_C6 timeout error interrupt is not recieved, meanwhile a new
    C6 could be triggered from IA and this could trigger a Ack_C6
    SCU can mistake this Ack_C6 as a ack for the previously aborted
    S0ix and continue S0ix flow. This is not correct.

    We check if the system is in S0ix progress state by checking
    scu_ready_sem if its already acquired that means S0ix is in
    progress and the subsequent C6 should be demoted to C4's

    Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date:   Sun May 22 11:57:12 2011 +0800

    Revert "mid_pmu:  Moving NC power management logic to OSPM"

    BZ: 2470

    This reverts commit 594c7f0327dd02985fbcde1e0bd83c98e684097f.

commit 594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date:   Thu May 12 10:51:38 2011 +0530

    mid_pmu:  Moving NC power management logic to OSPM

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state.
    This API will take care of talking to P-unit and getting the corresponding power
    islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit 4d0d20d8deda873a1e027ec2710675f58d2e9c7a
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date:   Thu May 5 10:01:30 2011 -0700

    GFX/PM: Export GFX APIs to power-gate NC IPs.
    BZ: 791
    Export GFX APIs (ospm_power_island_up/down) to be used by GFX, Video & Camera driver to power-gate NC IPs.

    Change-Id: Iadbc9513bf90df952063ef148245fbcf6d451dd7
    Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit 37c03045efcd790183acdbd3cb94db59566bdb6d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Mon Mar 21 14:47:53 2011 +0100

    mid_pmu: allow several devices to be on the same lss

    HSU devices are in HW in the same lss.
    There is a workaround in IAFW, that will not advertise the correct lss
    for HSU0 and HSU1. This does not solve anything, as HSU0 driver will start
    to make fabric errors as soon as HSU2 is suspended.

    We generically solve the issue by maintaining a table of devices
    present in the same lss. For such very short list, we do not take the
    overhead of using linked list. but rather use a 4 slots table for each lss.

    This patch contains ss hardcode for HSU0 and HSU1. To be removed when
    IAFW remove the bad workaround.

    Change-Id: I11240c225edc92984cca7e5e176bbebab6df2d5d
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon Jan 17 08:22:32 2011 +0100

    mid_pmu: driver that controls pmus of intel_mid platforms

    Mobile Internet Devices based on the Intel "Medfield" platform have two
    Platform Management Units (PMU). The first PMU (pmu1) comprises of the
    Silverthorne CPU, Graphics, Video encode/decode and Display engines,
    The second PMU (pmu2) is the IO hub.

    The Platform Management Unit (PMU) driver is a Medfield-specific power
    management driver. Intel's  MID provides fine tuned knobs for
    platform level. Intel's Medfield MID provides control for platform
    level power management and the OS Power Management solution guides the
    power states that the subsystems and CPU needs to be in depending on the
    current usage and power policy set by the user.

    The purpose of the Medfield Power Management architecture is to turn
    off subsystems without affecting the end user functionality/usability of
    the system.

    The Power Management scheme uses the concept of operating modes, which
    define the configuration of all the subsystems under each of the usage model
    that the user might put the system in. Based on current platform usage,
    OSPM decides the target power states for the sub systems, and the PMU
    driver implements the OS-HW interface.

    "Intel" Medfield PMU driver interfaces with two power management units
    (PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
    with the pmu1 & pmu2 via a well defined register interface to drive the
    required power  management flows.

    This patch contains:
    - key definitions for the PMU driver.
    - core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
    different platform power management flows.

    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
    Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>