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armv8: ls1028a: Updated serdes configuration for 0x13BB
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Wed, 4 Sep 2019 06:25:44 +0000 (06:25 +0000)
committerPriyanka Jain <priyanka.jain@nxp.com>
Thu, 12 Sep 2019 10:45:42 +0000 (16:15 +0530)
commit116f75c7b310bb5087195416e309d5a292e04560
tree53fd86aa38d28853e8c351cc2d96ed4be5bba36atree | snapshot
parentc9ba88bafc786a258f64ce673fc63b9e5994c88acommit | diff
armv8: ls1028a: Updated serdes configuration for 0x13BB

In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes
     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c diff | blob | history
Domain: System / Kernel;