[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
authorMatthew Malcomson <matthew.malcomson@arm.com>
Thu, 9 May 2019 09:29:17 +0000 (10:29 +0100)
committerMatthew Malcomson <matthew.malcomson@arm.com>
Thu, 9 May 2019 09:29:17 +0000 (10:29 +0100)
commit116adc27470ed3682b6236e44e3b18838673036c
treef3d401952aff1a968fb8466cb38b2b6a6d00500d
parent3bd82c86f0f432bd7653101069bf056fda14b7cd
[binutils][aarch64] New SVE_Zm3_11_INDEX operand.

Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
gas/ChangeLog
gas/config/tc-aarch64.c
include/ChangeLog
include/opcode/aarch64.h
opcodes/ChangeLog
opcodes/aarch64-asm-2.c
opcodes/aarch64-dis-2.c
opcodes/aarch64-opc-2.c
opcodes/aarch64-opc.c
opcodes/aarch64-opc.h
opcodes/aarch64-tbl.h