[ARM] generate correct code for armv6-m XO big stack operations
authorTies Stuij <ties.stuij@arm.com>
Tue, 4 Jul 2023 08:25:58 +0000 (09:25 +0100)
committerTies Stuij <ties.stuij@arm.com>
Tue, 4 Jul 2023 09:40:06 +0000 (10:40 +0100)
commit112d769e5ee8b7e961122ead3943f06119c05c5b
tree9ed78d57d3137c47746a86baca7f869365ae1ab1
parent1538ad9fc0140584c1569220f8c0b8c1c75c6578
[ARM] generate correct code for armv6-m XO big stack operations

The ARM backend codebase is dotted with places where armv6-m will generate
constant pools. Now that we can generate execute-only code for armv6-m, we need
to make sure we use the movs/lsls/adds/lsls/adds/lsls/adds pattern instead of
these.

Big stacks is one of the obvious places. In this patch we take care of two
sites:
1. take care of big stacks in prologue/epilogue
2. take care of save/tSTRspi nodes, which implicitly fixes
   emitThumbRegPlusImmInReg which is used in several frame lowering fns

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D154233
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/test/CodeGen/ARM/large-stack.ll