[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Tue, 4 Oct 2016 06:59:23 +0000 (06:59 +0000)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Tue, 4 Oct 2016 06:59:23 +0000 (06:59 +0000)
commit11049f8f07330c30c689d54ed91d63909b360cf2
treea70b349635cb8c9c5d445cc77595f2794e5e0dc4
parent6b929d5ba91eec2acd6f47c6921ce0dff9a94cd6
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions

This patch corresponds to review:
https://reviews.llvm.org/D23155

This patch removes the VSHRC register class (based on D20310) and adds
exploitation of the Power9 sub-word integer loads into VSX registers as well
as vector sign extensions.
The new instructions are useful for a few purposes:

    Int to Fp conversions of 1 or 2-byte values loaded from memory
    Building vectors of 1 or 2-byte integers with values loaded from memory
    Storing individual 1 or 2-byte elements from integer vectors

This patch implements all of those uses.

llvm-svn: 283190
33 files changed:
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCCallingConv.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
llvm/test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
llvm/test/CodeGen/PowerPC/machine-combiner.ll
llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll
llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
llvm/test/CodeGen/PowerPC/sjlj.ll
llvm/test/CodeGen/PowerPC/vsx-args.ll
llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll
llvm/test/CodeGen/PowerPC/vsx-p8.ll
llvm/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll [new file with mode: 0644]
llvm/test/CodeGen/PowerPC/vsx-spill-norwstore.ll
llvm/test/CodeGen/PowerPC/vsx-vec-spill.ll [new file with mode: 0644]
llvm/test/CodeGen/PowerPC/vsx.ll