[RISC-V] Fixed alias for addi x2, x2, 0
authorAna Pazos <apazos@codeaurora.org>
Thu, 9 Aug 2018 20:51:53 +0000 (20:51 +0000)
committerAna Pazos <apazos@codeaurora.org>
Thu, 9 Aug 2018 20:51:53 +0000 (20:51 +0000)
commit10de234905ea9dd310cb3047c7b9aa6c460c5653
tree60d3b609304482abae80224092a630cc09f4d6fd
parent03406c50faa9d8f8a731551318644db2831bfa01
[RISC-V] Fixed alias for addi x2, x2, 0

A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

llvm-svn: 339381
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/test/MC/RISCV/rv32c-aliases-valid.s