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clk: tegra: Unlock top rates for Tegra124 DFLL clock
authorMikko Perttunen <mikko.perttunen@kapsi.fi>
Tue, 15 Sep 2015 09:55:15 +0000 (12:55 +0300)
committerThierry Reding <treding@nvidia.com>
Tue, 15 Sep 2015 10:54:39 +0000 (12:54 +0200)
commit10d9be6ebe9199feb7680433a24b564a31a8f9b1
tree16a3843c12fcd7c9e9dc75ee49dd57dd525fc650tree | snapshot
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357fcommit | diff
clk: tegra: Unlock top rates for Tegra124 DFLL clock

The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.

Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-dfll.c diff | blob | history
drivers/clk/tegra/cvb.c diff | blob | history
Domain: System / Kernel;