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(parent: 5bd0ca1) | patch
Add support for the G33, Q33, and Q35 chipsets.
authorWang Zhenyu <zhenyu.z.wang@intel.com>
Tue, 5 Jun 2007 18:15:29 +0000 (11:15 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 5 Jun 2007 18:15:29 +0000 (11:15 -0700)
commit109e2a10f260f3a5f78762bbedcaeb9b2ebde1c0
tree6b968ef48f9a3592bdcc801d09c58bc0d081ebcftree | snapshot
parent5bd0ca125ed687b2dc6896197c0c8ab2673897f8commit | diff
Add support for the G33, Q33, and Q35 chipsets.

These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory.  So, we have the X Server allocate that memory and tell
us the address, instead.
shared-core/drm_pciids.txt diff | blob | history
shared-core/i915_dma.c diff | blob | history
shared-core/i915_drm.h diff | blob | history
shared-core/i915_drv.h diff | blob | history
Domain: System / Kernel;