author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000) | ||
commit | 1094e6a81430e76f0a6b836f52fa6e21726f5e6d | |
tree | 87d2a20519bf242b9b6ad12c58bd715a556b1130 | tree | snapshot |
parent | 732149b24eb3451ad4c4065327dfe1cefb40bad6 | commit | diff |
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | diff | blob | history | |
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | diff | blob | history | |
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir | [new file with mode: 0644] | blob |