drm/i915/tgl: Add definitions for VRR registers and bits
authorAditya Swarup <aditya.swarup@intel.com>
Thu, 19 Mar 2020 01:59:41 +0000 (18:59 -0700)
committerManasi Navare <manasi.d.navare@intel.com>
Fri, 27 Mar 2020 23:30:24 +0000 (16:30 -0700)
commit106d4ffd6cb8f15f3b66c0f64c16dfeda4f395e2
tree5da0f9a6ea005df9b848222f41bc62e3d57ab458
parent35f3fd8182ba26e766f7b814e903acf19d01bbb5
drm/i915/tgl: Add definitions for VRR registers and bits

Add definitions for registers grouped under Transcoder VRR function
with necessary bitfields.

Bspec: 49268

v2: Use REG_GENMASK, correct tabs/space indentation and move the
definitions near the transcoder section.(Jani)

v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)

v4: Use 'trans' in macro for better readability.(Manasi)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200319015941.28008-1-aditya.swarup@intel.com
drivers/gpu/drm/i915/i915_reg.h