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(parent: a9c45ce) | patch
RISC-V: Add vloxei32 C API intrinsic testcases
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Sun, 29 Jan 2023 15:48:46 +0000 (23:48 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 30 Jan 2023 16:42:28 +0000 (00:42 +0800)
commit106bd09fd1ffdfdb430073e513935b9c9a9dad2d
tree2acdd1a6033c80d0a18a330410dac1025353b372tree | snapshot
parenta9c45ce56a55c8a35724bb141276ef316ceed133commit | diff
RISC-V: Add vloxei32 C API intrinsic testcases

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vloxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-3.c: New test.
18 files changed:
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_m-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_m-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_m-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_mu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_mu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_mu-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tu-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tum-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tum-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tum-3.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tumu-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tumu-2.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/base/vloxei32_v_tumu-3.c [new file with mode: 0644] blob
Domain: System / Toolchain;