MIPS: mipsregs.h: Reindent CP0 Cause macros
authorMaciej W. Rozycki <macro@linux-mips.org>
Fri, 3 Apr 2015 22:23:56 +0000 (23:23 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 7 Apr 2015 23:08:39 +0000 (01:08 +0200)
commit1054533a322204042344b563012421e2dff6104d
treebb6fcacd44170399e9d20477d13abbc515e04b01
parente08384cad86b5ddd78ff8ef3262e846a1c4b2faa
MIPS: mipsregs.h: Reindent CP0 Cause macros

Reindent CP0 Cause macros for a single space after #define, leaving
extra indentation for individual Interrupt Pending bits as with CP0
Status register's Interrupt Mask bits.

[ralf@linux-mips.org: Fix conflict.]
[ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI
definitions.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mipsregs.h