drm/i915/guc: add steering info to GuC register save/restore list
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Mon, 14 Mar 2022 23:42:02 +0000 (16:42 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 16 Mar 2022 02:46:58 +0000 (19:46 -0700)
commit10343606ad287d2b8d8ebce0a5cebe5e877f341c
tree973c12a3a0bfceb3771b9528a7e6c85467f91357
parentb7563ec7d906ef87dcd15f39c66e0f35f58c2003
drm/i915/guc: add steering info to GuC register save/restore list

GuC has its own steering mechanism and can't use the default set by i915,
so we need to provide the steering information that the FW will need to
save/restore registers while processing an engine reset. The GUC
interface allows us to do so as part of the register save/restore list
and it requires us to specify the steering for all multicast register, even
those that would be covered by the default setting for cpu access. Given
that we do not distinguish between registers that do not need steering and
registers that are guaranteed to work the default steering, we set the
steering for all entries in the guc list that do not require a special
steering (e.g. mslice) to the default settings; this will cost us a few
extra writes during engine reset but allows us to keep the steering
logic simple.

Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220314234203.799268-3-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_gt.c
drivers/gpu/drm/i915/gt/intel_gt.h
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h