target-arm: A64: Add last AdvSIMD Integer to FP ops
authorAlex Bennée <alex.bennee@linaro.org>
Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)
commit10113b6903c0256c1741918430b0304c5a60b7a8
tree83b6c459fa064cefa1ddb2c1d38fb354ae5d1ca0
parentcf4ab1af296b8ef5d5a1dc65fda804b88ddd0553
target-arm: A64: Add last AdvSIMD Integer to FP ops

This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org
[PMM: added scalar 2-misc and scalar-shift-imm encodings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm/translate-a64.c