MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O
authorPaul Burton <paul.burton@imgtec.com>
Wed, 9 Jul 2014 11:51:05 +0000 (12:51 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 30 Jul 2014 18:49:36 +0000 (20:49 +0200)
commit0fc0708a8a2e6ff5e9ab633185903831fe478994
tree069a9907d8ab37b65d2c03a6525f812a201d636f
parentc90e49f26466d1733558b8385f4755a6ee3ddafc
MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O

The dma_cache_wback_inv function performs exactly as is required here,
unless the system has coherent I/O in which case it's a no-op. Call the
underlying cache writeback functions directly, which is arguably clearer
anyway given that the code doesn't actually have anything to do with
DMA in a strict sense.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7282/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/smp-cps.c