projects / platform / upstream / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 06cdf22) | patch
radv: adjust alignment of the preprocess buffer with DGC
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 21 Jun 2023 11:07:34 +0000 (13:07 +0200)
committerMarge Bot <emma+marge@anholt.net>
Fri, 23 Jun 2023 17:17:08 +0000 (17:17 +0000)
commit0f8864e04713db0000f1f41458737314ddd9f512
treeecae134433c855329c2b3300fc380b0b41139a97tree | snapshot
parent06cdf222a6c3052eed6510d14b962dd8775769d4commit | diff
radv: adjust alignment of the preprocess buffer with DGC

The preprocess buffer is the buffer used to generate the cmdbuf. It
was aligned to 256 bytes but the correct alignment is actually
ac_gpu_info::ib_alignment.

Otherwise, if a DGC IB is executed like a IB1, this hits an assertion
in radv_amdgpu_cs_submit() because the alignment is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23764>
src/amd/vulkan/radv_device_generated_commands.c diff | blob | history
Domain: Graphics System / GL;