Revert "ARM: sti: Implement dummy L2 cache's write_sec"
authorPatrice Chotard <patrice.chotard@st.com>
Thu, 18 Jun 2020 17:24:56 +0000 (19:24 +0200)
committerArnd Bergmann <arnd@arndb.de>
Sun, 28 Jun 2020 12:46:54 +0000 (14:46 +0200)
commit0f77ce26ebcf6ea384421d2dd47b924b83649692
tree99dd5a9129118c58cc01d28a643ede9421783950
parent4c9f47ce57b807003e83d7cbeee77e3c10a26ac6
Revert "ARM: sti: Implement dummy L2 cache's write_sec"

This reverts commit 7b8e0188fa717cd9abc4fb52587445b421835c2a.

Initially, STiH410-B2260 was supposed to be secured, that's why
l2c_write_sec was stubbed to avoid secure register access from
non secure world.

But by default, STiH410-B2260 is running in non secure mode,
so L2 cache register accesses are authorized, l2c_write_sec stub
is not needed.

With this patch, L2 cache is configured and performance are enhanced.

Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Alain Volmat <alain.volmat@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/mach-sti/board-dt.c