AMDGPU/SI: Don't reserve XNACK when it's disabled
authorMarek Olsak <marek.olsak@amd.com>
Fri, 9 Dec 2016 19:49:54 +0000 (19:49 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Fri, 9 Dec 2016 19:49:54 +0000 (19:49 +0000)
commit0f55fbae6c7f40938b27571a20752a376ae49eb1
tree528ef08804bc9a7243957b77561bef09bacbb01b
parent693e9be9181eb8b3cc91e254a2acb49accafbd9c
AMDGPU/SI: Don't reserve XNACK when it's disabled

Summary:
This frees 2 additional scalar registers.

These are results from all of my 3 patches combined:

  Polaris:
    Spilled SGPRs: 2231 -> 1517 (-32.00 %)

  Tonga:
    Spilled SGPRs: 3829 -> 2608 (-31.89 %)
    Spilled VGPRs: 100 -> 84 (-16.00 %)

  Tonga even spills SGPRs via VGPRs to scratch. That's a compute shader
  limited to 64 VGPRs.

Reviewers: tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27151

llvm-svn: 289262
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll