projects / platform / upstream / gcc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b0241ce) | patch
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Fri, 20 Jan 2023 09:33:09 +0000 (17:33 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 27 Jan 2023 09:59:08 +0000 (17:59 +0800)
commit0f024ff988aeaacd8d0f967c5f841ab20fb40c19
treea951342912671194d655a179b2e166433853bee1tree | snapshot
parentb0241ce6e37031e1cbde73d5389ec7f1d063e099commit | diff
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes

According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
gcc/config/riscv/vector-iterators.md diff | blob | history
Domain: System / Toolchain;