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(parent: 2d7bb60) | patch
[InstCombine] reduce compare of signbits of 2 values, signed variant
authorSanjay Patel <spatel@rotateright.com>
Wed, 25 Jan 2023 21:27:29 +0000 (16:27 -0500)
committerSanjay Patel <spatel@rotateright.com>
Thu, 26 Jan 2023 13:58:45 +0000 (08:58 -0500)
commit0ef7cbc319ee6488a47fda1b45b0d7170722df31
treec43fb17796ef99d4c8e02068f89cc1104a16d362tree | snapshot
parent2d7bb6066722d894591360464608698e9125bdffcommit | diff
[InstCombine] reduce compare of signbits of 2 values, signed variant

(X s>> BitWidth - 1) == sext (Y s> -1) --> (X ^ Y) < 0
(X s>> BitWidth - 1) != sext (Y s> -1) --> (X ^ Y) > -1

This is the same logic as:
7cbfc39c77ca
...extended to deal with "signed" cast+shift instructions.

https://alive2.llvm.org/ce/z/LLidya
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp diff | blob | history
llvm/test/Transforms/InstCombine/icmp-shr.ll diff | blob | history
Domain: System / Toolchain;