clk: axg: add pll enable op [1/1]
authorQiufang Dai <qiufang.dai@amlogic.com>
Thu, 13 Jul 2017 06:20:54 +0000 (14:20 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Thu, 13 Jul 2017 07:59:09 +0000 (00:59 -0700)
commit0ec1fea28c5569ad3bc59792ee07669aef222293
tree06b37cf1755ed0b1362be3528dee395a7b8f66d1
parent1ed4152d43338ffb8353596b29c29e0e5258d63f
clk: axg: add pll enable op [1/1]

PD#146411: add enable op for pcie_gp0/hifi/mpll pll

Change-Id: I15eb279a0bf00035d2053322179dddc5d8d9d213
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
drivers/amlogic/clk/axg/axg_clk-pll.c
drivers/amlogic/clk/clk-mpll.c