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author	Simon Pilgrim <llvm-dev@redking.me.uk>
	Tue, 23 Jul 2019 15:35:55 +0000 (15:35 +0000)
committer	Simon Pilgrim <llvm-dev@redking.me.uk>
	Tue, 23 Jul 2019 15:35:55 +0000 (15:35 +0000)
commit	0e8359aec108be4bf794681ba477c7ffb00095d8
tree	59c99d383fe67768aee9b518b8183c3b4dcc6444	tree \| snapshot
parent	aa4f8d04a967e889838211e00b9ba7fc0c07846f	commit \| diff

[TargetLowering] SimplifyMultipleUseDemandedBits - add VECTOR_SHUFFLE support.

If all the demanded elts are from one operand and are inline, then we can use the operand directly.

The changes are mainly from SSE41 targets which has blendvpd but not cmpgtq, allowing the v2i64 comparison to be simplified as we only need the signbit from alternate v4i32 elements.

llvm-svn: 366817

24 files changed:

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp		diff \| blob \| history
llvm/test/CodeGen/X86/midpoint-int-vec-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/psubus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/sat-add.ll		diff \| blob \| history
llvm/test/CodeGen/X86/uadd_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/usub_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_minmax_sint.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_minmax_uint.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-rot-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-rot-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-smin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-packus-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-packus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-ssat-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-ssat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-usat-widen.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-usat.ll		diff \| blob \| history

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