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[mips][msa] Implement f16 support
authorSimon Dardis <simon.dardis@imgtec.com>
Fri, 18 Nov 2016 16:17:44 +0000 (16:17 +0000)
committerSimon Dardis <simon.dardis@imgtec.com>
Fri, 18 Nov 2016 16:17:44 +0000 (16:17 +0000)
commit0e2ee3b4b98327bf9a5c2fa4707f8a1983c9950a
tree9e53468e83d881d68e237eb7445ab9dd8ebbfb8ctree | snapshot
parent7bde5df5f0b9daa2eaa23e467d689d05c5530df7commit | diff
[mips][msa] Implement f16 support

The MIPS MSA ASE provides instructions to convert to and from half precision
floating point. This patch teaches the MIPS backend to treat f16 as a legal
type and how to promote such values to f32 for the usual set of operations.

As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during
type legalization.

Reviewers: zoran.jovanvoic, vkalintiris

Differential Revision: https://reviews.llvm.org/D26398

llvm-svn: 287349
llvm/lib/Target/Mips/MipsMSAInstrInfo.td diff | blob | history
llvm/lib/Target/Mips/MipsRegisterInfo.td diff | blob | history
llvm/lib/Target/Mips/MipsSEISelLowering.cpp diff | blob | history
llvm/lib/Target/Mips/MipsSEISelLowering.h diff | blob | history
Domain: System / Toolchain;