RISC-V: Fix wrong RTL pattern for ternary instructions.

RISC-V: Fix wrong RTL pattern for ternary instructions.

We've wrong RTL pattern cause unexpected optimizaion result.

Give a example is vnmsub.vx pattern, the operation of vnmsub.vx
list below:

  vnmsub.vx vd, rs1, vs2, vm    # vd[i] = -(x[rs1] * vd[i]) + vs2[i]

But our RTL pattern write as (x[rs1] * vd[i]) - vs2[i], and the GCC try to
simplify when x[rs1] is constant 1, and then become a vd[i] - vs[i]
instruction.

We also revise all ternary instructions to make sure the RTL has right
semantic:

And it's the mapping list between instruction and RTL pattern:

interger:
vnmsac.vv vd, vs1, vs2, vm    # vd[i] = -(vs1[i] * vs2[i]) + vd[i]  (minus op3 (mult op1 op2))
vnmsac.vx vd, rs1, vs2, vm    # vd[i] = -(x[rs1] * vs2[i]) + vd[i]   (minus op3 (mult op1 op2))

floating-point:
vfmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3)
vfmacc.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3)

vfnmacc.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2))) op3))
vfnmacc.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2)) op3))
vfmsac.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3)
vfmsac.vf vd, rs1, vs2, vm    # vd[i] = +(f[rs1] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3)

vfnmsac.vv vd, vs1, vs2, vm   # vd[i] = -(vs1[i] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3)
vfnmsac.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3)

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Fix ternary bug.
	* config/riscv/vector-iterators.md (nmsac): Ditto.
	(nmsub): Ditto.
	(msac): Ditto.
	(msub): Ditto.
	(nmadd): Ditto.
	(nmacc): Ditto.
	* config/riscv/vector.md (@pred_mul_<optab><mode>): Ditto.
	(@pred_mul_plus<mode>): Ditto.
	(*pred_madd<mode>): Ditto.
	(*pred_macc<mode>): Ditto.
	(*pred_mul_plus<mode>): Ditto.
	(@pred_mul_plus<mode>_scalar): Ditto.
	(*pred_madd<mode>_scalar): Ditto.
	(*pred_macc<mode>_scalar): Ditto.
	(*pred_mul_plus<mode>_scalar): Ditto.
	(*pred_madd<mode>_extended_scalar): Ditto.
	(*pred_macc<mode>_extended_scalar): Ditto.
	(*pred_mul_plus<mode>_extended_scalar): Ditto.
	(@pred_minus_mul<mode>): Ditto.
	(*pred_<madd_nmsub><mode>): Ditto.
	(*pred_nmsub<mode>): Ditto.
	(*pred_<macc_nmsac><mode>): Ditto.
	(*pred_nmsac<mode>): Ditto.
	(*pred_mul_<optab><mode>): Ditto.
	(*pred_minus_mul<mode>): Ditto.
	(@pred_mul_<optab><mode>_scalar): Ditto.
	(@pred_minus_mul<mode>_scalar): Ditto.
	(*pred_<madd_nmsub><mode>_scalar): Ditto.
	(*pred_nmsub<mode>_scalar): Ditto.
	(*pred_<macc_nmsac><mode>_scalar): Ditto.
	(*pred_nmsac<mode>_scalar): Ditto.
	(*pred_mul_<optab><mode>_scalar): Ditto.
	(*pred_minus_mul<mode>_scalar): Ditto.
	(*pred_<madd_nmsub><mode>_extended_scalar): Ditto.
	(*pred_nmsub<mode>_extended_scalar): Ditto.
	(*pred_<macc_nmsac><mode>_extended_scalar): Ditto.
	(*pred_nmsac<mode>_extended_scalar): Ditto.
	(*pred_mul_<optab><mode>_extended_scalar): Ditto.
	(*pred_minus_mul<mode>_extended_scalar): Ditto.
	(*pred_<madd_msub><mode>): Ditto.
	(*pred_<macc_msac><mode>): Ditto.
	(*pred_<madd_msub><mode>_scalar): Ditto.
	(*pred_<macc_msac><mode>_scalar): Ditto.
	(@pred_neg_mul_<optab><mode>): Ditto.
	(@pred_mul_neg_<optab><mode>): Ditto.
	(*pred_<nmadd_msub><mode>): Ditto.
	(*pred_<nmsub_nmadd><mode>): Ditto.
	(*pred_<nmacc_msac><mode>): Ditto.
	(*pred_<nmsac_nmacc><mode>): Ditto.
	(*pred_neg_mul_<optab><mode>): Ditto.
	(*pred_mul_neg_<optab><mode>): Ditto.
	(@pred_neg_mul_<optab><mode>_scalar): Ditto.
	(@pred_mul_neg_<optab><mode>_scalar): Ditto.
	(*pred_<nmadd_msub><mode>_scalar): Ditto.
	(*pred_<nmsub_nmadd><mode>_scalar): Ditto.
	(*pred_<nmacc_msac><mode>_scalar): Ditto.
	(*pred_<nmsac_nmacc><mode>_scalar): Ditto.
	(*pred_neg_mul_<optab><mode>_scalar): Ditto.
	(*pred_mul_neg_<optab><mode>_scalar): Ditto.
	(@pred_widen_neg_mul_<optab><mode>): Ditto.
	(@pred_widen_mul_neg_<optab><mode>): Ditto.
	(@pred_widen_neg_mul_<optab><mode>_scalar): Ditto.
	(@pred_widen_mul_neg_<optab><mode>_scalar): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/bug-3.c: New test.
	* gcc.target/riscv/rvv/base/bug-4.c: New test.
	* gcc.target/riscv/rvv/base/bug-5.c: New test.

Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>