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(parent: 59aea37) | patch
mips: octeon: Initial minimal support for the Marvell Octeon SoC
authorAaron Williams <awilliams@marvell.com>
Tue, 30 Jun 2020 10:08:56 +0000 (12:08 +0200)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Sat, 18 Jul 2020 13:47:50 +0000 (15:47 +0200)
commit0dc4ab9c43ff6a235b4c0c5295a1a9747ea684c9
tree27c647c9fbc99170c2761f28d434e8431f668304tree | snapshot
parent59aea37abf6bf6d5119a9e2f0237b26bf820b285commit | diff
mips: octeon: Initial minimal support for the Marvell Octeon SoC

This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
14 files changed:
MAINTAINERS diff | blob | history
arch/mips/Kconfig diff | blob | history
arch/mips/Makefile diff | blob | history
arch/mips/mach-octeon/Kconfig [new file with mode: 0644] blob
arch/mips/mach-octeon/Makefile [new file with mode: 0644] blob
arch/mips/mach-octeon/cache.c [new file with mode: 0644] blob
arch/mips/mach-octeon/clock.c [new file with mode: 0644] blob
arch/mips/mach-octeon/cpu.c [new file with mode: 0644] blob
arch/mips/mach-octeon/dram.c [new file with mode: 0644] blob
arch/mips/mach-octeon/include/ioremap.h [new file with mode: 0644] blob
arch/mips/mach-octeon/include/mach/cavm-reg.h [new file with mode: 0644] blob
arch/mips/mach-octeon/include/mach/clock.h [new file with mode: 0644] blob
arch/mips/mach-octeon/lowlevel_init.S [new file with mode: 0644] blob
scripts/config_whitelist.txt diff | blob | history
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