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R600: Fix LowerSDIV24
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Jul 2014 06:59:20 +0000 (06:59 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Jul 2014 06:59:20 +0000 (06:59 +0000)
commit0daeb63f036c48b20c7149d877b72381cc08fd4d
tree49fb6e6e8ff44c186f32c9776270c17ee1f8ea37tree | snapshot
parent459dec0ca2a765fc7fa6bc24b662a5e10df18e97commit | diff
R600: Fix LowerSDIV24

Use ComputeNumSignBits instead of checking for i8 / i16 which only
worked when AMDIL was lying about having legal i8 / i16.

If an integer is known to fit in 24-bits, we can
do division faster with float ops.

llvm-svn: 213843
llvm/lib/Target/R600/AMDGPUISelLowering.cpp diff | blob | history
llvm/test/CodeGen/R600/sdiv24.ll [new file with mode: 0644] blob
Domain: System / Toolchain;