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(parent: ac51e00) | patch
riscv: gcov: enable gcov for RISC-V
authorZong Li <zong.li@sifive.com>
Thu, 2 Jan 2020 03:09:54 +0000 (11:09 +0800)
committerPaul Walmsley <paul.walmsley@sifive.com>
Fri, 3 Jan 2020 08:47:02 +0000 (00:47 -0800)
commit0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe
treef8e5eeb96d120146213c3421f7f05b65b67f8dd2tree | snapshot
parentac51e005fe1456a288929a41d71adc6224e912d2commit | diff
riscv: gcov: enable gcov for RISC-V

This patch enables GCOV code coverage measurement on RISC-V.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Documentation/features/debug/gcov-profile-all/arch-support.txt diff | blob | history
arch/riscv/Kconfig diff | blob | history
Domain: System / Kernel;