Refine movhfcc.
authorliuhongt <hongtao.liu@intel.com>
Fri, 8 Oct 2021 07:21:44 +0000 (15:21 +0800)
committerliuhongt <hongtao.liu@intel.com>
Sat, 9 Oct 2021 01:26:43 +0000 (09:26 +0800)
commit0d788c358b94d0e1983e0c6bf6269fa105b6d007
tree0391350a980a9a32c3b14aefc6fb65c287cc3e70
parentce6eec392647046167e7dfecd3dfdd07012b8931
Refine movhfcc.

For AVX512-FP16, HFmode only supports vcmpsh whose dest is mask
register, so for movhfcc, it's

vcmpsh op2, op1, %k1
vmovsh op1, op2{%k1}
mov op2, dest

gcc/ChangeLog:

PR target/102639
* config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Handle
HFmode.
(ix86_use_mask_cmp_p): Ditto.
(ix86_expand_sse_movcc): Ditto.
* config/i386/i386.md (setcc_hf_mask): New define_insn.
(movhf_mask): Ditto.
(UNSPEC_MOVCC_MASK): New unspec.
* config/i386/sse.md (UNSPEC_PCMP): Move to i386.md.

gcc/testsuite/ChangeLog:
* g++.target/i386/pr102639.C: New test.
gcc/config/i386/i386-expand.c
gcc/config/i386/i386.md
gcc/config/i386/sse.md
gcc/testsuite/g++.target/i386/pr102639.C [new file with mode: 0644]