[PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update...
authorAmy Kwan <amy.kwan1@ibm.com>
Fri, 28 Jan 2022 15:26:12 +0000 (09:26 -0600)
committerAmy Kwan <amy.kwan1@ibm.com>
Tue, 1 Feb 2022 14:48:37 +0000 (08:48 -0600)
commit0d6e64755acf0334f9a3958c254b32ac95aa859b
tree901c3868816a752dd18a25982c3d5ec353b4c596
parent89275300d861aef73225428c95fdb069de36186d
[PowerPC] Update P10 vector insert patterns to use refactored load/stores, and update handling of v4f32 vector insert.

This patch updates the P10 patterns with a load feeding into an insertelt to
utilize the refactored load and store infrastructure, as well as updating any
tests that exhibit any codegen changes.

Furthermore, custom legalization is added for v4f32 on Power9 and above to not
only assist with adjusting the refactored load/stores for P10 vector insert,
but also it enables the utilization of direct moves.

Differential Revision: https://reviews.llvm.org/D115691
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
llvm/test/CodeGen/PowerPC/vec_insert_elt.ll