clk: meson-gxbb: Add GXL/GXM GP0 Variant
authorNeil Armstrong <narmstrong@baylibre.com>
Wed, 22 Mar 2017 10:32:25 +0000 (11:32 +0100)
committerKevin Hilman <khilman@baylibre.com>
Tue, 4 Apr 2017 19:05:14 +0000 (12:05 -0700)
commit0d48fc558d01ded71ffad3fe6cca8081847ac9a7
treec46ffb1692c940c1c280e158c1046b26de69ae49
parente194401cf4d49e7fe2f8ec994130d59e94f09137
clk: meson-gxbb: Add GXL/GXM GP0 Variant

The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM
SoCs embeds a different GP0 PLL, and needs different parameters with a vendor
provided reduced rate table.

This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order
to use the GXL GP0 PLL instead of the GXBB specific one.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com
drivers/clk/meson/gxbb.c
drivers/clk/meson/gxbb.h