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(parent: e4080e7) | patch
Add the following 64-bit vector integer arithmetic instructions added in POWER8:
authorKit Barton <kbarton@ca.ibm.com>
Tue, 3 Mar 2015 19:55:45 +0000 (19:55 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Tue, 3 Mar 2015 19:55:45 +0000 (19:55 +0000)
commit0cfa7b7ad035cd349be419b8601748bfcb1edf1b
tree72c9cbc1f3a1cea152cd4a34c89f613fa35f761dtree | snapshot
parente4080e7f2ab886dbe3c03777e1573be66c8bb07acommit | diff
Add the following 64-bit vector integer arithmetic instructions added in POWER8:

vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959

llvm-svn: 231115
13 files changed:
llvm/include/llvm/IR/IntrinsicsPowerPC.td diff | blob | history
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff | blob | history
llvm/lib/Target/PowerPC/PPCSchedule.td diff | blob | history
llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff | blob | history
llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/vec_cmpd.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/vec_minmax.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/vec_mul_even_odd.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/vec_rotate_shift.ll [new file with mode: 0644] blob
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt diff | blob | history
llvm/test/MC/PowerPC/ppc64-encoding-vmx.s diff | blob | history
Domain: System / Toolchain;