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(parent: 45810d4) | patch
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
authorSwapnil Jakhade <sjakhade@cadence.com>
Mon, 3 Apr 2023 08:56:44 +0000 (10:56 +0200)
committerVinod Koul <vkoul@kernel.org>
Wed, 12 Apr 2023 16:36:26 +0000 (22:06 +0530)
commit0cfa43ab46b577804a3e89cc5aa7922fe4d9b74f
treec61b432d34809d0895cd35a375a205f135ad49a7tree | snapshot
parent45810d486bb44bd60213d5f09a713df81b987972commit | diff
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
Domain: System / Kernel;