PCI: qcom: Add IPQ60xx support
authorSelvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
Tue, 21 Jun 2022 08:54:54 +0000 (11:54 +0300)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 15 Jul 2022 20:30:57 +0000 (15:30 -0500)
commit0cf7c2efe8ac76bb6b90abc64bcf8df124509d7d
treeaeafaa4311fa4b2178fcc5e0158a378f778ab6bf
parent9a765805f62aa590fd4281740b4ef75425c0b12b
PCI: qcom: Add IPQ60xx support

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch
win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI
registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il
Tested-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
drivers/pci/controller/dwc/pcie-designware.h
drivers/pci/controller/dwc/pcie-qcom.c