[TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.
authorCraig Topper <craig.topper@sifive.com>
Sat, 19 Dec 2020 22:25:16 +0000 (14:25 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sat, 19 Dec 2020 22:56:17 +0000 (14:56 -0800)
commit0cbceed27c491ebd185e1f53bd0f43ce655efceb
tree6b64646c4367c3504ccb63cbb75a196fbc6edf7f
parent99930719c66df9a8b67f3575d251b182c9cc8ee9
[TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.

These properties aren't additive. They are closer to ReadOnly and
WriteOnly. The default is ReadWrite. ReadMem cancels the write property and
WriteMem cancels the read property. Combining them leaves neither.

This patch checks that when we process WriteMem, the Mod flag is
still set. And for ReadMem we check that the Ref flag set still set.

I've updated 2 target intrinsics that were combining these properties.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D93571
28 files changed:
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/test/tools/llvm-mca/X86/Atom/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
llvm/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s
llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
llvm/test/tools/llvm-mca/X86/BtVer2/stmxcsr-ldmxcsr.s
llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Haswell/stmxcsr-ldmxcsr.s
llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s
llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-sse1.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
llvm/utils/TableGen/CodeGenTarget.cpp